This invention relates to an electronic timepiece including a liquid-crystal unit adapted to be operated in either one of a normal time count mode or a stopwatch time count mode in response to a switching operation.
Electronic timepieces are known which include an alternating type liquid-crystal display unit of static or dynamic variety adapted to alternately apply positive and negative voltages to liquid-crystal segments. Out of these, an electronic timepiece is known which has the double function of: (1) counting seconds, minutes, hours, days or dates, etc. and displaying an appropriate time count value; and (2) counting any time interval for example, t.sub.1 to t.sub.2, and displaying its time count value (i.e., stopwatch function). Such type of electronic timepiece will be explained by referring to FIGS. 1 to 3.
In the electronic timepiece circuit shown in FIG. 1 an output signal from a crystal oscillator 1 is frequency divided by a frequency divider 2 into a 1 Hz signal. The output signal of the frequency divider 2 is supplied sequentially to a scale of ten counter 3, scale of 6 counter 4, scale of ten counter 5, scale of six counter 6, scale of ten counter 7 and scale of six counter 8 in this order. The output signals of the counters 3 to 8 are supplied respectively through AND gates 9 to 14 to decoders 15 to 20, where they are decoded. The numerical data corresponding to the output signals of the decoders 15 to 20 are displayed on a display device 21.
The output signal of the oscillator 1 is also supplied through an AND gate 22 to a frequency divider 23 where it is frequency divided into a 100 Hz signal. The 100 Hz output signal of the frequency divider 23 is sequentially supplied to the scale of ten counters 24, 25 and 26, scale of six counter 27, scale of ten counter 28 and scale of six counter 29 in this order. The outputs of these counters 24 to 29 are supplied respectively through AND gates 30 to 35 to decoders 36 to 41 where they are decoded. The numerical data corresponding to the output signal of the decoders 36 to 41 may also be displayed on the display device 21. It is to be understood that the output lines from the counters 3-8 and 24-29 actually include a plurality (e.g., four) of bit channels for transmitting, for example, a binary coded decimal (BCD) digit. Similarly, AND gates 9-14 and 30-35 actually include a plurality of AND circuits (as shown in FIG. 2) for gating the multi-channel counter outputs in parallel to the decoders.
The Q output terminal of a flip-flop circuit 42 whose state is switched by a switch SW1 is connected to the other terminal of each of the AND gates 9 to 14, and the Q output terminal of the flip-flop circuit 42 is connected to the other input terminal of the AND gates 30 to 35. The Q output terminal of a flip-flop circuit 43 whose state is switched by a switch SW2 is connected to the other terminal of the AND gate 22. The counters 24 to 29 are reset when the flip-flop circuit 42 is set by the operation of the switch SW1 into a state in which a normal time count is executed. In the circuit shown in FIG. 1 the decoders 36 to 41 may be omitted and, instead, the output terminals of the AND gates 30 to 35 be connected to the decoders 15 to 20 through OR gates connected to the output terminals of the AND gates 9 to 14.
Where it is desired to set the electronic timepiece of FIG. 1 into the normal time count operation mode the flip-flop circuit 42 is set by the operation of the switch SW1 to cause the AND gates 9 to 14 to be enabled. Where it is desired to set the electronic timepiece into the stopwatch operation mode the flip-flop circuit 42 is reset by the operation of the switch SW1, causing the AND circuits 30 to 35 to be enabled. Then, the flip-flop circuit 43 is set by the operation of the switch SW2 to cause the AND gate 22 to be enabled. In the stopwatch operation mode a time continuously varying in units of a 1/100 second is displayed in a 1/100-second digit display section.
Where in the stopwatch operation mode the unit of time to be counted is equal to, or smaller than, the cycle of a common input signal (LCM signal) of a dynamic drive type liquid-crystal display unit, if such a time count data varying at such a small time interval is displayed, a voltage applied to the liquid-crystal display device has a total of polarity time intervals of one polarity in a predetermined period of time which is unbalanced with respect to the total of polarity time intervals of the opposite polarity which occur in the same period of time, as will be later described.
In the circuit shown in FIG. 2 the scale of ten counter 24 is driven by a 100 Hz output pulse from the frequency divider 23 of FIG. 1 and the count data bits of the counter 24 are supplied through AND gates 30-1 to 30-4 to the 1/100 digit decoder 36, i.e., the decoder for the diplay digit in the 0.01 second digit position. The decoder 36 decodes the count signals of the scale of ten counter 24. The decoded signals of the decoder 36 are supplied through exclusive OR circuits 44 to 50 to a display section 21-1. By so doing, a count value corresponding to a 1/100-second digit is displayed on a 7-segment pattern on the display section 21-1, the seven segments being arranged in a figure-of-"8" pattern and facing a common electrode. The LCM signal is supplied to the other input terminal of each of the exclusive OR circuits 44 to 50 and to the common electrode.
FIG. 3 shows a signal waveform diagram for explaining the operation of the circuit of FIG. 2. The waveform P1 illustrates the 100 Hz output pulse signal of the frequency divider 23 for frequency dividing output pulses from the oscillator 1. A crystal oscillator normally used for electronic timepiece generates a 32.768 KHz output pulse signal and the output pulse signal of the crystal oscillator is frequency divided by a normal frequency divider down to a 100 Hz pulse signal. The waveform of the pulse signal is irregular as will be understood from the waveform P1. The waveform P2 illustrates a 32 Hz LCM signal to be applied to the common electrode of the display section. Waveform P3 illustrates a data signal supplied from the decoder 36 to the exclusive OR circuit 47 when the counter 24 has its contents counted up in response to the pulse signal as indicated by the waveform P1, i.e., when the contents of the counter 24 are varied from "0" to "9" in accordance with 10 pulse signals from the frequency divider 23. As shown relative to the P1 waveform, the first positive transition in the pulse train switches counter 24 to the zero state and the leading edge of every tenth pulse thereafter returns the count to zero. Five decimal counting cycles are depicted by the P1 pulse train. The P3 data signal shows a high level "H" (a display state) when the content of the counter 24 is "0", "2", "3", "5", "6", "8" or "9" and a low level "L" (a non-display state) when the content of the counter 24 is "1", "4" or "7". Waveform P4 shows the segment signal supplied from the exclusive OR circuit 47 to control the lower segment LS in the display section 21-1 (FIG. 2). Waveform P5 shows the voltage level of the segment LS of the display section 21-1 responsive to exclusive OR 41 with respect to the common voltage. As will be understood from the waveform, the segment signal shows a "0" when the content of the counter 24 is "1", "4" or "7" and it is not lighted. It is desired that the integrated valve of this signal over a predetermined period of time be zero. However, the total of positive voltage time intervals in one second of the segment signal P5 for the example shown in the FIG. 2 circuit is 343.750 milliseconds, while the total of negative voltage time intervals in that period of the segment signal is 390.625 milliseconds. The total of zero voltage time intervals is 265.625 milliseconds. In such segment signal, therefore, the total of the negative voltage time intervals is 46.875 milliseconds longer than the total of the positive voltage time intervals for each second. That is, during a time interval corresponding to about 5% of the total stopwatch operation mode interval one polarity of the DC voltage, for example, the negative polarity is equivalently applied to the liquid-crystal, thereby shortening the service life of the liquid-crystal display device.